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Summary: Low-cost Protection for SER Upsets and Silicon Defects
Mojtaba Mehrara Mona Attariyan Smitha Shyam Kypros Constantinides
Valeria Bertacco Todd Austin
Advanced Computer Architecture Lab
University of Michigan, Ann Arbor, MI 48109
{mehrara,monattar,smithash,kypros,valeria,austin}@umich.edu
ABSTRACT
Extreme transistor scaling trends in silicon technology are
soon to reach a point where manufactured systems will suffer
from limited device reliability and severely reduced life-time,
due to early transistor failures, gate oxide wear-out, manu-
facturing defects, and radiation-induced soft errors (SER).
In this paper we present a low-cost technique to harden a
microprocessor pipeline and caches against these reliabil-
ity threats. Our approach utilizes online built-in self-test
(BIST) and microarchitectural checkpointing to detect, di-
agnose and recover the computation impaired by silicon de-
fects or SER events. The approach works by periodically
testing the processor to determine if the system is broken.
If so, we reconfigure the processor to avoid using the bro-
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