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Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory
 

Summary: Direct Coherence: Bringing Together
Performance and Scalability in Shared-Memory
Multiprocessors
Alberto Ros, Manuel E. Acacio, and Jos´e M. Garc´ia
Departamento de Ingenier´ia y Tecnolog´ia de Computadores
Universidad de Murcia, 30100 Murcia (Spain)
{a.ros,meacacio,jmgarcia}@ditec.um.es
Abstract. Traditional directory-based cache coherence protocols suffer
from long-latency cache misses as a consequence of the indirection intro-
duced by the home node, which must be accessed on every cache miss
before any coherence action can be performed. In this work we present a
new protocol that moves the role of storing up-to-date coherence infor-
mation (and thus ensuring totally ordered accesses) from the home node
to one of the sharing caches. Our protocol allows most cache misses to be
directly solved from the corresponding remote caches, without requiring
the intervention of the home node. In this way, cache miss latencies are
reduced. Detailed simulations show that this protocol leads to improve-
ments in total execution time of 8% on average over a highly optimized
MOESI directory-based protocol.
1 Introduction

  

Source: Acacio, Manuel - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia

 

Collections: Computer Technologies and Information Sciences