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VLSI DESIGN OF MULTI STANDARD TURBO DECODER FOR 3G AND BEYOND Imran Ahmed, Tughrul Arslan
 

Summary: 6B-4
VLSI DESIGN OF MULTI STANDARD TURBO DECODER FOR 3G AND BEYOND
Imran Ahmed, Tughrul Arslan
School ofElectronics and Engineering. University ofEdinburgh, King's Buildings Mayfield Rd, Edinburgh, EH9 3JL, UK
Institute for System Level Integration, The Alba Campus, The Alba Centre, Livingston, Scotland, EH54 7EG, UK
MESSAGE BITS
BEFORE
ENCODING COMPONENT
DECODER1ABSTRACT
Turbo decoding architectures have greater error correcting
capability than any other known code. Due to their
excellent performance turbo codes have been employed in
several transmission systems such as CDMA2000,
WCDMA (UMTS), ADSL, IEEE 802.16 metropolitan
networks etc. The computation kernel of the algorithm is
very similar and we have exploited this commonality for a
turbo decoder VLSI design suitable for deployment using
platform based system on chip methodologies. Turbo and
viterbi components ofthe unified array are also individually
reconfigurable for different standards. This supports the 4G

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering