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A CMOS LOW-POWER LOW-OFFSET AND HIGH-SPEED FULLY DYNAMIC LATCHED COMPARATOR
 

Summary: A CMOS LOW-POWER LOW-OFFSET AND HIGH-SPEED FULLY
DYNAMIC LATCHED COMPARATOR
HeungJun Jeon, Yong-Bin Kim
Northeastern University
Boston, MA, USA
hjeon@ece.neu.edu, ybk@ece.neu.edu
ABSTRACT
This paper presents a novel dynamic latched
comparator that demonstrates lower offset voltage
and higher load drivability than the conventional
dynamic latched comparators. With two additional
inverters inserted between the input- and output-stage
of the conventional double-tail dynamic comparator,
the gain preceding the regenerative latch stage is
improved. The complementary version of the
regenerative latch stage, which provides larger output
drive current than the conventional one at a limited
area, is implemented. The proposed circuit is
designed using 90nm CMOS technology and 1V
power supply voltage, and it demonstrates up to 19%

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering