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IEE Colloquim on Low Power Analogue and Digital VLSI: ASICs, Techniques and Applications, 2 June 1995, pp. 493498. OVERVIEW AND DESIGN DIRECTIONS FOR LOWPOWER CIRCUITS AND ARCHITECTURES FOR
 

Summary: IEE Colloquim on Low Power Analogue and Digital VLSI: ASICs, Techniques and Applications, 2 June 1995, pp. 493­498.
OVERVIEW AND DESIGN DIRECTIONS FOR LOW­POWER CIRCUITS AND ARCHITECTURES FOR
DIGITAL SIGNAL PROCESSING
T. Arslan, D.H. Horrocks, and A.T. Erdogan 1
1. Introduction
Power dissipation is becoming a limiting factor in the realisation of VLSI systems. The principal reasons for
this are maximum operating temperature and, for portable applications, battery life. Because of the relatively
greater complexity, the power dissipation in Digital Signal Processing (DSP) applications is of special
significance, and low­power design techniques are now emerging.
This paper provides an overview of these techniques and aims to serve as a bibliography of the key papers
relevant to low­power DSP design. In addition, the paper presents indications for potential design directions
bearing in mind the architectural complexity and the speed requirements of today's systems.
CMOS logic is assumed since this is currently the most commonly used VLSI technology due to its high
degree of integration which is in turn allowed by its scaling properties and low power dissipation.
2. Power Dissipation in Digital CMOS Circuits
The main sources of power dissipation, in a typical CMOS digital circuit (Figure 1), are given by the
following equation:
P P P P
ave s sc
= + + (1),

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering