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Summary: Streamlining Data Cache Access with
Fast Address Calculation
Todd M. Austin Dionisios N. Pnevmatikatos Gurindar S. Sohi
Computer Sciences Department
University of Wisconsin-Madison
1210 W. Dayton Street
Madison, WI 53706
faustin,pnevmati,sohig@cs.wisc.edu
Abstract
For many programs, especially integer codes, untolerated load in-
struction latencies account for a significant portion of total execution
time. In this paper, we present the design and evaluation of a fast
address generation mechanism capable of eliminating the delays
caused by effective address calculation for many loads and stores.
Our approach works by predicting early in the pipeline (part of) the
effective address of a memory access and using this predicted address
to speculatively access the data cache. If the prediction is correct,
the cache access is overlapped with non-speculative effective address
calculation. Otherwise, the cache is accessed again in the following
cycle, this time using the correct effective address. The impact on the
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