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978-1-4244-6455-5/10/$26.00 2010 IEEE 99 11th Int'l Symposium on Quality Electronic Design A Novel All-Digital Fractional-N Frequency Synthesizer Architecture
 

Summary: 978-1-4244-6455-5/10/$26.00 2010 IEEE 99 11th Int'l Symposium on Quality Electronic Design
A Novel All-Digital Fractional-N Frequency Synthesizer Architecture
with Fast Acquisition and Low Spur
Jun Zhao, Yong-Bin Kim
Department of ECE, Northeastern University, USA
{jzhao, ybk}@ece.neu.edu
Abstract
Digital implementation of analog function is becoming
attractive in CMOS ICs, given the low supply voltage of
ultra-scaled process. The conventional fractional-N
frequency synthesizers suffer form the fractional spur due to
the application of fractional divider. A new architecture of an
all digital fractional-N phase-locked loop based frequency
synthesizer is presented in this paper. The unique feature of
the proposed frequency synthesizer is application of an extra
time-to-digital converter (TDC) to measure the fractional
value. The proposed Fraction-N frequency synthesizer is
implemented using 32nm CMOS Predictive Technology
Model (PTM) at 0.9V supply voltage. In the implementation
example, input reference frequency is 300 MHz, frequency

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering