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Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture
 

Summary: 6B-3
Implementation of a Real Time Programmable Encoder for Low Density
Parity Check Code on a Reconfigurable Instruction Cell Architecture
Zahid Khan, Tughrul Arslan
System Level Integration Group,
The University ofEdinburgh,
Mayfield Road, Edinburgh, EH9 3JL, Scotland, UK
Abstract - This paper presents a real time programmable
irregular Low Density Parity Check (LDPC) Encoder as
specified in the IEEE P802.16E/D7 standard. The encoder is
programmable for frame sizes from 576 to 2304 and for five
different code rates. H matrix is efficiently generated and stored
for a particular frame size and code rate. The encoder is
implemented on Reconfigurable Instruction Cell Architecture
(RA) which has recently emerged as an ultra low power, high
performance, ANSI-C programmable embedded core. Different
general and architecture specific optimization techniques are
applied to enhance the throughput. With RA, a throughput from
10 to 19 Mbps has been achieved.
I. Introduction

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering