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A Second-Generation Sensor Network Processor with Application-Driven Memory Optimizations
 

Summary: A Second-Generation Sensor Network Processor
with Application-Driven Memory Optimizations
and Out-of-Order Execution
Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson,
Todd Austin and David Blaauw
The University of Michigan
1301 Beal Ave, Ann Arbor, MI 48109
subliminal@eecs.umich.edu
ABSTRACT
In this paper we present a second-generation sensor network processor
which consumes less than one picoJoule per instruction (typical processors
use 100s to 1000s of picoJoules per instruction). As in our first-generation
design effort, we strive to build microarchitectures that minimize area to re-
duce leakage, maximize transistor utility to reduce the energy-optimal volt-
age, and optimize CPI for efficient processing. The new design builds on our
previous work to develop a low-power subthreshold-voltage sensor proces-
sor, this time improving the design by focusing on ISA, memory system de-
sign, and microarchitectural optimizations that reduce overall design size
and improve energy-per-instruction. The new design employs 8-bit data-
paths and an ultra-compact 12-bit wide RISC instruction set architecture,

  

Source: Austin, Todd M. - Department of Electrical Engineering and Computer Science, University of Michigan

 

Collections: Engineering; Computer Technologies and Information Sciences