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Exploiting Vector Parallelism in Software Pipelined Loops Samuel Larsen, Rodric Rabbah and Saman Amarasinghe
 

Summary: Exploiting Vector Parallelism in Software Pipelined Loops
Samuel Larsen, Rodric Rabbah and Saman Amarasinghe
MIT Computer Science and Artificial Intelligence Laboratory
{slarsen,rabbah,saman}@mit.edu
Abstract
An emerging trend in processor design is the addition
of short vector instructions to general-purpose and embed-
ded ISAs. Frequently, these extensions are employed us-
ing traditional vectorization technology first developed for
supercomputers. In contrast, scalar hardware is typically
targeted using ILP techniques such as software pipelin-
ing. This paper presents a novel approach for exploiting
vector parallelism in software pipelined loops. The pro-
posed methodology (i) lowers the burden on the scalar re-
sources by offloading computation to the vector functional
units, (ii) explicitly manages communication of operands
between scalar and vector instructions, (iii) naturally han-
dles misaligned vector memory operations, and (iv) par-
tially (or fully) inhibits the optimization when vectorization
will decrease performance.

  

Source: Amarasinghe, Saman - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)

 

Collections: Computer Technologies and Information Sciences