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Enhancing Simulation with BDDs and ATPG Malay K. Ganai Adnan Aziz

Summary: Enhancing Simulation with BDDs and ATPG
Malay K. Ganai Adnan Aziz
Electrical and Computer Engineering
The University of Texas at Austin
Andreas Kuehlmann
IBM Thomas J. Watson Research Center
Yorktown Heights, NY, USA
We introduce SImulation Veri cation with Augmentation
(SIVA), a tool for checking safety properties on digital hard-
ware designs. SIVA integrates simulation with symbolic tech-
niques for vector generation. Speci cally, the core algorithm
uses a combination of ATPG and BDDs to generate input
vectors which cover behavior not excited by simulation. Ex-
perimental results demonstrate considerable improvement in
state space coverage compared with either simulation or for-
mal veri cation in isolation.
Keywords: Formal veri cation, ATPG, simulation, BDDs,


Source: Aziz, Adnan - Department of Electrical and Computer Engineering, University of Texas at Austin


Collections: Computer Technologies and Information Sciences