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Summary: Complexity Effective Memory Access Scheduling for
Many-Core Accelerator Architectures
George L. Yuan Ali Bakhoda Tor M. Aamodt
Department of Electrical and Computer Engineering
University of British Columbia, Vancouver, BC, CANADA
{gyuan,bakhoda,aamodt}@ece.ubc.ca
ABSTRACT
Modern DRAM systems rely on memory controllers that
employ out-of-order scheduling to maximize row access lo-
cality and bank-level parallelism, which in turn maximizes
DRAM bandwidth. This is especially important in graphics
processing unit (GPU) architectures, where the large quan-
tity of parallelism places a heavy demand on the memory
system. The logic needed for out-of-order scheduling can
be expensive in terms of area, especially when compared to
an in-order scheduling approach. In this paper, we propose
a complexity-effective solution to DRAM request schedul-
ing which recovers most of the performance loss incurred by
a naive in-order first-in first-out (FIFO) DRAM scheduler
compared to an aggressive out-of-order DRAM scheduler.
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