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A New Biasing Technique for the MOS Transistor Munir A. Al-Absi
 

Summary: A New Biasing Technique for the MOS Transistor
Munir A. Al-Absi
Electrical Engineering Department
King Fahd University for Petroleum and Minerals, Dhahran, Saudi Arabia, 31261
mkulaib@kfupm.edu.sa
Abstract: - This paper describes a new biasing technique for the MOS transistor. The MOS is biased by a
Gate-to-Bulk voltage VGB. The value of VGB can be chosen according to the level of inversion required, strong
or weak. The input signal, current or voltage can be fed from either the drain or the source terminal. The
technique can be sued in the implementation of logarithmic and antilogarithmic functions with microampere
current range. This in turn will enhance the speed of the device in this mode of operation compared to the
traditional weak inversion biasing. The new approach was verified by simulation using HSPICE level 47 in
0.8um CMOS process.
Key-Words: - Biasing Weak inversion Strong inversion Logarithmic Antilogarithmic
1 Introduction
It is well known MOS transistor are usually biased
using fixed gate-to-source voltage VGS. The MOS is a
four terminal device and in many applications the bulk
terminal is connected to the least potential for nMOS
and to the highest potential for the pMOS. Some
powerful circuits were designed using bulk-to-source

  

Source: Al-Absi, Munir A. - Electrical Engineering Department, King Fahd University of Petroleum and Minerals

 

Collections: Engineering