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> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 CNTFET-Based Design of Ternary Logic Gates
 

Summary: > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1
CNTFET-Based Design of Ternary Logic Gates
and Arithmetic Circuits
Sheng Lin, Student Member, IEEE, Yong-Bin Kim, Senior Member, IEEE, and Fabrizio Lombardi,
Fellow, IEEE
Abstract--This paper presents a novel design of ternary logic
gates using carbon nanotube FETs (CNTFETs). Ternary logic is a
promising alternative to the conventional binary logic design
technique since it is possible to accomplish simplicity and energy
efficiency in modern digital design due to the reduced circuit
overhead such as interconnects and chip area. A resistive-load
CNTFET-based ternary logic design has been proposed to
implement ternary logic based on CNTFET. In this paper, a novel
design technique for ternary logic gates based on CNTFETs is
proposed and compared with the existing resistive load CNTFET
logic gate designs. Especially, the proposed ternary logic gate
design technique combined with the conventional binary logic
gate design technique provides an excellent speed and power
consumption characteristics in datapath circuit such as full adder
and multiplier. Extensive simulation results using SPICE are

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering