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Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures
 

Summary: Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in
Future Embedded CMP Architectures
Antonio Flores, Juan L. Arag´on and Manuel E. Acacio
Departamento de Ingenier´ia y Tecnolog´ia de Computadores
Facultad de Inform´atica. Campus de Espinardo S/N - 30100. Murcia (Spain)
{aflores, jlaragon, meacacio}@ditec.um.es
Abstract
Continuous improvements in integration scale have
made major microprocessor vendors to move to designs
that integrate several processor cores on the same chip.
Chip-multiprocessors (CMPs) constitute the architecture of
choice in the high performance embedded domain for sev-
eral reasons such as better levels of scalability and perfor-
mance/energy ratio. On the other hand, higher clock fre-
quencies and increasing transistor density have revealed
power dissipation as a critical design issue, especially in
embedded systems where reduced energy consumption di-
rectly translates into extended battery life. In this work
we present Sim-PowerCMP, a detailed architecture-level
power-performance simulation tool for CMP architectures

  

Source: Acacio, Manuel - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia

 

Collections: Computer Technologies and Information Sciences