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This paper presents pipelined implementation of a real time programmable irregular Low Density Parity
 

Summary: Abstract
This paper presents pipelined implementation of a real
time programmable irregular Low Density Parity
Check (LDPC) Encoder as specified in the IEEE
P802.16E/D7 standard. The encoder is programmable
for frame sizes from 576 to 2304 and for five different
code rates. H matrix is efficiently generated and stored
for a particular frame size and code rate. The encoder
is implemented on Reconfigurable Instruction Cell
Architecture which has recently emerged as an ultra
low power, high performance, ANSI-C programmable
embedded core. Different general and architecture
specific optimization techniques are applied to enhance
the throughput. With the architecture, a throughput
from 10 to 19 Mbps has been achieved. The maximum
throughput achieved with pipelining/ multi-core is 78
Mbps.
1. Introduction
Low Density Parity Check (LDPC) codes are attributed
to Gallager who proposed them in his 1960 PhD

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering