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A Comparative Study of Two Boolean Formulations of
 

Summary: A Comparative Study of
Two Boolean Formulations of
FPGA Detailed Routing Constraints
Gi-Joon Nam, Member, IEEE, Fadi Aloul,
Karem A. Sakallah, Fellow, IEEE, and Rob A. Rutenbar, Fellow, IEEE
Abstract--This paper presents empirical analyses of two Boolean Satisfiability (SAT) formulations of FPGA (Field Programmable
Gate Array) detailed routing constraints. Boolean SAT-based routing transforms a routing problem into a Boolean SAT instance by
rendering geometric routing constraints as an atomic Boolean function. The generated Boolean function is satisfiable if and only if the
corresponding routing is possible. Two different Boolean SAT-based routing models are analyzed: the track-based and the route-
basedrouting constraint model. The track-based routing model transforms a routing task into a net-to-track assignment problem,
whereas the route-based routing model reduces it into a routability-checking problem with explicitly enumerated set of detailed routes
for nets. In both models, routing constraints are represented as CNF Boolean Satisfiability clauses. Through comparative experiments,
we demonstrate that the route-based formulation yields an easier-to-evaluate and more scalable routability Boolean function than the
track-based method. This is empirical evidence that a smart/efficient Boolean formulation can achieve significant performance
improvement in real-world applications.
Index Terms--Boolean Satisfiability, FPGAs, routing physical design.

1 INTRODUCTION
THE Boolean Satisfiability problem (SAT) involves finding
an assignment to binary variables that satisfies a given

  

Source: Aloul, Fadi - Department of Computer Engineering, American University of Sharjah

 

Collections: Engineering