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IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 17, NO. 3, MAY 2006 745 Exploiting Application Locality to Design
 

Summary: IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 17, NO. 3, MAY 2006 745
Exploiting Application Locality to Design
Low-Complexity, Highly Performing, and
Power-Aware Embedded Classifiers
Cesare Alippi, Fellow, IEEE, and Fabio Scotti, Member, IEEE
Abstract--Temporal and spatial locality of the inputs, i.e., the
property allowing a classifier to receive the same samples over
time--or samples belonging to a neighborhood--with high prob-
ability, can be translated into the design of embedded classifiers.
The outcome is a computational complexity and power aware
design particularly suitable for implementation. A classifier based
on the gated-parallel family has been found particularly suitable
for exploiting locality properties: Subclassifiers are generally
small, independent each other, and controlled by a master-en-
abling module granting that only a subclassifier is active at a time,
the others being switched off. By exploiting locality properties we
obtain classifiers with accuracy comparable with the ones designed
without integrating locality but gaining a significant reduction in
computational complexity and power consumption.
Index Terms--Application-level design, classifier design, em-

  

Source: Alippi, Cesare - Dipartimento di Elettronica e Informazione, Politecnico di Milano

 

Collections: Computer Technologies and Information Sciences