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Summary: Heuristic Symmetry Reduction for Invariant Verification
William Hung Adnan Aziz Ken McMillan
Electrical and Computer Engineering Cadence Berkeley Labs
The University of Texas Cadence
Austin TX Berkeley CA
Abstract
We describe techniques that use symmetry to perform effi
cient invariant checking. We start by developing the the
ory needed to exploit symmetry for designs specified at the
gate level. This is followed by a proof of the inadequacy
of BDD based methods for highly symmetric designs; this
motivates the use of explicit state enumeration. Exact sym
metry reduction has been conjectured to be computationally
intractable; we propose fast heuristic reduction procedures.
Experiments with these routines demonstrate their effective
ness in practice; we also compare running times with a BDD
based tool.
1 Introduction
A common problem in formal verification of hardware de
signs is to determine if every state reachable from the reset
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