Summary: E. Macii et al. (Eds.): PATMOS 2004, LNCS 3254, pp. 585­592, 2004.
© Springer-Verlag Berlin Heidelberg 2004
A Dual Low Power and Crosstalk Immune Encoding
Scheme for System-on-Chip Buses
Zahid Khan
1
, Tughrul Arslan
1,2
, and Ahmet T. Erdogan
1
1
University of Edinburgh, Scotland,UK
Z.Khan@ed.ac.uk
2
Institute for System Level Integration livingston, Scotland
Abstract. Crosstalk causes logical errors due to data dependent delay degrada-
tion as well as energy consumption and is considered the biggest signal integ-
rity challenge for long on-chip buses implemented in Ultra Deep Submicron
CMOS technology. Elimination or minimization of crosstalk is crucial to the
performance and reliability of SoC designs. This paper presents a novel on-chip

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

Collections: Engineering