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Published in the Proceedings of the 26th International Symposium on Computer Architecture, May 1999. A Scalable Front-End Architecture for Fast Instruction Delivery
 

Summary: Published in the Proceedings of the 26th International Symposium on Computer Architecture, May 1999.
A Scalable Front-End Architecture for Fast Instruction Delivery
Glenn Reinmany
Todd Austinz
Brad Caldery
y
Department of Computer Science and Engineering, University of California, San Diego
z
Microcomputer Research Labs, Intel Corporation
Abstract
In the pursuit of instruction-level parallelism, signifi-
cant demands are placed on a processor's instruction de-
livery mechanism. Delivering the performance necessary to
meet future processor execution targets requires that the per-
formance of the instruction delivery mechanism scale with
the execution core. Attaining these targets is a challenging
task due to I-cache misses, branch mispredictions, and taken
branches in the instruction stream. To further complicate
matters, a VLSI interconnect scaling trend is materializing
that further limits the performance of front-end designs in

  

Source: Austin, Todd M. - Department of Electrical Engineering and Computer Science, University of Michigan
Calder, Bradley - Department of Computer Science and Engineering, University of California at San Diego
Sair, Suleyman - Department of Electrical and Computer Engineering, North Carolina State University

 

Collections: Computer Technologies and Information Sciences; Engineering