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Regular Model Checking for S1S + LTL Parosh Aziz Abdulla, Bengt Jonsson, Marcus Nilsson, Julien d'Orso, and
 

Summary: Regular Model Checking for S1S + LTL
Parosh Aziz Abdulla, Bengt Jonsson, Marcus Nilsson, Julien d'Orso, and
Mayank Saksena
Dept. of Information Technology, P.O. Box 337, S-751 05 Uppsala, Sweden
fparosh,bengt,marcusn,juldor,mayanksg@it.uu.se
Abstract. Regular model checking is a form of symbolic model check-
ing for parameterized and in nite-state systems whose states can be rep-
resented as words of arbitrary length over a nite alphabet, in which
regular sets of words are used to represent sets of states. We present
LTL(S1S), a combination of the logics S1S and LTL as an ideal logic for
expressing temporal properties to be veri ed in regular model checking.
LTL(S1S) is a two-dimensional modal logic, where S1S is used for spec-
ifying properties of system states and transitions, and LTL is used for
specifying temporal properties. In addition, the rst-order quanti cation
in S1S can be used to express properties parameterized on a position
or process. We give a technique for model checking LTL(S1S), which is
adapted from the automata-theoretic approach: a formula is translated
to a (Buchi) transducer with a regular set of accepting states, and reg-
ular model checking techniques are used to search for models. We have
implemented the technique and show its application to a number of pa-

  

Source: Abdulla, Parosh Aziz - Department of Information Technology, Uppsala Universitet

 

Collections: Computer Technologies and Information Sciences