Summary: Asynchronous Multithreaded Processor Cores for System
D. K. Arvind and R. Rangaswami
Division of Informatics, The University of Edinburgh,
Edinburgh EH9 3JZ, United Kingdom.
A radical alternative based on an asynchronous design methodology is proposed for the design
of future system level integration devices. An asynchronous multithreaded processor core is
presented along with glimpses into some design issues for a multithreaded Java bytecode com
piler. Such a platform expoits concurrency at different levels: between coarsegrained threads
running on a multinode processor, between mediumgrained threads running on the thread pro
cessing units in each processor node, and between finegrained threads running on the functional
units in each thread processing unit. Such as platform implemented using an asynchronous design
methodology is capable of delivering high performance at a competitive power consumption.
System Level Integration (SLI) is defined as the design, analysis and implementation of integ
rated software and hardware systems in silicon. It is widely believed that an SLI device should
contain at least a processor core with accompanying embedded software, onchip memory, and
interfaces to offchip peripherals. It might also incorporate other features such as onchip buses,