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Asynchronous Multithreaded Processor Cores for System Level Integration
 

Summary: Asynchronous Multithreaded Processor Cores for System
Level Integration
D. K. Arvind and R. Rangaswami
Division of Informatics, The University of Edinburgh,
Edinburgh EH9 3JZ, United Kingdom.
E­mail: dka,ror@dcs.ed.ac.uk
Abstract
A radical alternative based on an asynchronous design methodology is proposed for the design
of future system level integration devices. An asynchronous multithreaded processor core is
presented along with glimpses into some design issues for a multithreaded Java byte­code com­
piler. Such a platform expoits concurrency at different levels: between coarse­grained threads
running on a multi­node processor, between medium­grained threads running on the thread pro­
cessing units in each processor node, and between fine­grained threads running on the functional
units in each thread processing unit. Such as platform implemented using an asynchronous design
methodology is capable of delivering high performance at a competitive power consumption.
1 Introduction
System Level Integration (SLI) is defined as the design, analysis and implementation of integ­
rated software and hardware systems in silicon. It is widely believed that an SLI device should
contain at least a processor core with accompanying embedded software, on­chip memory, and
interfaces to off­chip peripherals. It might also incorporate other features such as on­chip buses,

  

Source: Arvind, D. K. - School of Informatics, University of Edinburgh

 

Collections: Computer Technologies and Information Sciences