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The Effect of Communication Time Delays in Parallel Computations
 

Summary: The Effect of Communication Time Delays in
Parallel Computations
C. T. Abdallah
ECE Dept, University of New Mexico
Alburquerque NM 87131-1356, USA
chaouki@eece.unm.edu
J. D. Birdwell, J. Chiasson
Z. Tang, N. Alluri
ECE Dept, University of Tennessee
Knoxville TN 37996, USA
birdwell@utk.edu, chiasson@utk.edu
tang@hickory.engr.utk.edu, nalluri@utk.edu
Tsewei Wang
ChE Dept, University of Tennessee
Knoxville TN 37996, USA, twang@utk.edu
July 5, 2002
1 Introduction
Parallel computer architectures utilize a set of computational elements (CE) to
achieve performance that is not attainable on a single processor, or CE, com-
puter. A common architecture is the cluster of otherwise independent computers

  

Source: Abdallah, Chaouki T- Electrical and Computer Engineering Department, University of New Mexico

 

Collections: Engineering