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Summary: Synthesizing Interconnect-Efficient Low Density
Parity Check Codes
Marghoob Mohiyuddin
The University of Texas at Austin
Amit Prakash
The University of Texas at Austin
Adnan Aziz
The University of Texas at Austin
Wayne Wolf
Princeton University
ABSTRACT
Error correcting codes are widely used in communication
and storage applications. Codec complexity has usually
been measured with a software implementation in mind.
A recent hardware implementation of a Low Density Par-
ity Check code (LDPC) indicates that interconnect com-
plexity dominates the VLSI cost. We describe a heuris-
tic interconnect-aware synthesis algorithm which generates
LDPC codes that use an order of magnitude less wiring with
little or no loss of coding efficiency.
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