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Copyright 1997 IEEE. Published in the Proceedings of Micro-30, December 1-3, 1997 in Research Triangle Park, North Carolina. Personal use of thismaterial is permitted. However, permission to reprint/republish this material
 

Summary: Copyright 1997 IEEE. Published in the Proceedings of Micro-30, December 1-3, 1997 in Research Triangle Park,
North Carolina. Personal use of thismaterial is permitted. However, permission to reprint/republish this material
for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or
lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE.Contact:
Manager, Copyrights and Permissions / IEEE Service Center / 445 Hoes Lane / P.O. Box 1331 / Piscataway, NJ
08855-1331, USA. Telephone: + Intl. 908-562-3966.
Improving the Accuracy and Performance of Memory
Communication Through Renaming
Gary S. Tyson
The University of Michigan
tyson@eecs.umich.edu
Todd M. Austin
Intel Microcomputer Research Labs
taustin@ichips.intel.com
Abstract
As processors continue to exploit more instruction
level parallelism, a greater demand is placed on reducing
the e ects of memory access latency. In this paper, we
introduce a novel modi cation of the processor pipeline
called memory renaming. Memory renaming applies

  

Source: Austin, Todd M. - Department of Electrical Engineering and Computer Science, University of Michigan

 

Collections: Engineering; Computer Technologies and Information Sciences