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Improving the Accuracy and Performance of Memory
Communication Through Renaming
Gary S. Tyson
The University of Michigan
tyson@eecs.umich.edu
Todd M. Austin
Intel Microcomputer Research Labs
taustin@ichips.intel.com
Abstract
As processors continue to exploit more instruction
level parallelism, a greater demand is placed on reducing
the e ects of memory access latency. In this paper, we
introduce a novel modi cation of the processor pipeline
called memory renaming. Memory renaming applies

Source: Austin, Todd M. - Department of Electrical Engineering and Computer Science, University of Michigan

Collections: Engineering; Computer Technologies and Information Sciences