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Summary: A fault-tolerant directory-based cache coherence protocol for CMP
architectures
Ricardo Fern´andez-Pascual, Jos´e M. Garc´ia, Manuel E. Acacio and Jos´e Duato
Universidad de Murcia, Spain. E-mail: {rfernandez,jmgarcia,meacacio}@ditec.um.es
Universidad Polit´ecnica de Valencia, Spain. E-mail: jduato@gap.upv.es
Abstract
Current technology trends of increased scale of in-
tegration are pushing CMOS technology into the deep-
submicron domain, enabling the creation of chips with a
significantly greater number of transistors but also more
prone to transient failures. Hence, computer architects
will have to consider reliability as a prime concern for
future chip-multiprocessor designs (CMPs). Since the
interconnection network of future CMPs will use a sig-
nificant portion of the chip real state, it will be especially
affected by transient failures. We propose to deal with
this kind of failures at the level of the cache coherence
protocol instead of ensuring the reliability of the net-
work itself. Particularly, we have extended a directory-
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