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Soft-Error Hardening Designs of Nanoscale CMOS Latches
 

Summary: Soft-Error Hardening Designs of Nanoscale
CMOS Latches
Sheng Lin, Yong-Bin Kim and Fabrizio Lombardi
Department of Electrical and Computer Engineering
Northeastern University
Boston, MA, USA
Abstract-- As technology scales down in the deep sub-
micron/nano ranges, CMOS circuits are more sensitive to
externally induced phenomena to likely cause the
occurrence of so-called soft errors. Therefore, the operation
of these circuits to tolerate soft errors is a strict requirement
in today's designs. Traditional error tolerant methods result
in significant cost penalties in terms of power, area and
performance, and the development of low-cost hardening
designs for storage cells (such as latches and memories) is of
increasing importance. This paper proposes new hardening
designs for CMOS latches at 32nm feature size. Three
hardening latch circuits are proposed; two of these circuits
are Schmitt trigger based, while the third one utilizes a
cascode configuration in the feedback loop. These new

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering