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Copyright 1999 IEEE. Appears in Proceedings of MICRO32, November 1999. Code Transformations to Improve Memory Parallelism \Lambda
 

Summary: Copyright 1999 IEEE. Appears in Proceedings of MICRO­32, November 1999.
Code Transformations to Improve Memory Parallelism \Lambda
Vijay S. Pai y and Sarita Adve z
y Electrical and Computer Engineering z Computer Science
Rice University University of Illinois
Houston, TX 77005 Urbana­Champaign, IL 61801
vijaypai@rice.edu sadve@cs.uiuc.edu
Abstract
Current microprocessors incorporate techniques to ex­
ploit instruction­level parallelism (ILP). However, previous
work has shown that these ILP techniques are less effective
in removing memory stall time than CPU time, making the
memory system a greater bottleneck in ILP­based systems
than previous­generation systems. These deficiencies arise
largely because applications present limited opportunities
for an out­of­order issue processor to overlap multiple read
misses, the dominant source of memory stalls.
This work proposes code transformations to increase
parallelism in the memory system by overlapping multiple
read misses within the same instruction window, while pre­

  

Source: Adve, Sarita - Department of Computer Science, University of Illinois at Urbana-Champaign

 

Collections: Computer Technologies and Information Sciences