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Summary: Energy-Efficient Hardware Prefetching for CMPs using Heterogeneous
Interconnects
Antonio Flores, Juan L. Arag´on and Manuel E. Acacio
Departamento de Ingenier´ia y Tecnolog´ia de Computadores
University of Murcia
Murcia, Spain
Email: {aflores, jlaragon, meacacio}@ditec.um.es
Abstract--In the last years high performance processor
designs have evolved toward Chip-Multiprocessor (CMP)
architectures that implement multiple processing cores on a
single die. As the number of cores inside a CMP increases, the
on-chip interconnection network will have significant impact
on both overall performance and power consumption as pre-
vious studies have shown. On the other hand, CMP designs
are likely to be equipped with latency hiding techniques like
hardware prefetching in order to reduce the negative impact
on performance that, otherwise, high cache miss rates would
lead to. Unfortunately, the extra number of network messages
that prefetching entails can drastically increase the amount
of power consumed in the interconnect. In this work, we show
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