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Proceedings Of The IEE Colloquium On Digital Synthesis, London, UK, pp.7/1-7/5, 15th Feb 1996. - 1996 IEE. Personal use of this material is permitted However, permission to reprint/republish this material for advertising or promotional purposes or for
 

Summary: Proceedings Of The IEE Colloquium On Digital Synthesis, London, UK, pp.7/1-7/5, 15th Feb 1996. - 1996 IEE. Personal use of
this material is permitted However, permission to reprint/republish this material for advertising or promotional purposes or for
creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work
in other works must be obtained from the IEE.
Genetic Synthesis Techniques for Low-Power Digital Signal Processing Circuits
T. Arslan, E Ozdemir, M. S. Bright, and D.H. Horrocks
University of Wales Cardiff
Cardiff CF2 1XH
Introduction
Power dissipation is becoming a limiting factor in the realisation of VLSI systems. The principal
reasons for this are maximum operating temperature and battery life for portable applications.
Because of the relatively greater complexity, the power dissipation in Digital Signal Processing (DSP)
applications is of special significance, and low-power design techniques are now emerging [1]. These
vary depending on the level of the design that they target, ranging from the semiconductor technology
to the higher algorithmic level.
This paper will describe two different techniques which employ Genetic Algorithms for synthesis of
digital circuits. The first employs a multi-objective genetic algorithm for synthesising low power
circuits. A gate-level description of the circuit is encoded into a single chromosome and the GA
evolves by searching for circuit structures that are optimised for both overall capacitive area and
critical path. This in turn will allow operation under reduced power supply voltages [1]. Although, the

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering