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IEEE International Symposium on Circuits and Systems (ISCAS'98), 31 May --3 June 1998, Monterey, CA, pp. D425D428. LOW POWER IMPLEMENTATION OF LINEAR PHASE FIR FILTERS
 

Summary: IEEE International Symposium on Circuits and Systems (ISCAS'98), 31 May -- 3 June 1998, Monterey, CA, pp. D425­D428.
1
LOW POWER IMPLEMENTATION OF LINEAR PHASE FIR FILTERS
FOR SINGLE MULTIPLIER CMOS BASED DSPs
A.T. Erdogan and T. Arslan
Cardiff University of Wales
Cardiff School of Engineering
Cardiff CF2 3TF, United Kingdom.
ERDOGAN@Cardiff.ac.uk, ARSLAN@Cardiff.ac.uk
ABSTRACT
Recently, a new scheme for the single multiplier
implementation of low power digital filters on CMOS­
based DSPs was presented [1,2]. In this paper the scheme
is generalised to include linear phase FIR filters (LPFIRs)
and its implementation is investigated with two common
methods of LPFIR realisation structures. The paper also
describes an effective framework which combines layout,
timing, and capacitive information, for the evaluation of
power consumption for FIR filters. New results are
provided which demonstrate up to 85% reduction in

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering