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IEE Electronics Letters, Vol. 32, No. 13, pp. 1150-1151, 20th June, 1996 - 1996 IEE. Personal use of this material is permitted However, permission to reprint/republish this material for advertising or promotional purposes or for creating
 

Summary: IEE Electronics Letters, Vol. 32, No. 13, pp. 1150-1151, 20th June, 1996 - 1996 IEE. Personal use of this material is
permitted However, permission to reprint/republish this material for advertising or promotional purposes or for creating
new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in
other works must be obtained from the IEE.
A Genetic Framework For The High-Level Optimisation Of Low Power
VLSI DSP Systems
M.S. Bright and T. Arslan
The University Of Wales Cardiff
Cardiff School Of Engineering
Cardiff CF2 1XH
UK
________________________________________________________
Abstract: This letter presents a technique for optimising CMOS based DSP systems for
power. A Genetic Algorithm is used to reduce power, while tracking area and speed
specifications, through the application of high level transformations. The algorithm searches
for systems with the lowest power consumption within a large solution space. Results are
presented which demonstrate the efficiency of the Genetic Algorithm as a power
optimisation tool for complex VLSI systems.
Introduction: Power dissipation has become an increasingly important parameter in the
realisation of VLSI systems. It is especially important in the rapidly expanding portable

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering