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Summary: Performance and Variability Optimization Strategies in a Sub-200mV, 3.5pJ/inst,
11nW Subthreshold Processor
Scott Hanson, Bo Zhai, Mingoo Seok, Brian Cline, Kevin Zhou, Meghna Singhal, Michael Minuth, Javin Olson, Leyla Nazhandali, Todd Austin,
Dennis Sylvester, David Blaauw, University of Michigan, Ann Arbor, MI
Abstract
A robust, energy efficient subthreshold (sub-Vth) processor has been
designed and tested in a 0.13µm technology. The processor con-
sumes 11nW at Vdd=160mV and 3.5pJ/inst at Vdd=350mV. Variabil-
ity and performance optimization techniques are investigated for
sub-Vth circuits.
Keywords: subthreshold, variability, body-bias, low power
Introduction
Recent progress in low voltage circuit design has created opportu-
nities for the development of inexpensive pervasive computing sys-
tems. Previous work has shown that minimum energy operation
typically occurs in the sub-Vth regime (Vdd
we describe a sub-Vth processor for sensor network applications. The
processor consumes 3.5pJ/inst at Vdd=350mV under zero body bias
and 11nW at Vdd=160mV under a reverse body bias. There are two
primary problems confronting sub-Vth designers: increased variabil-
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