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Classifying Load and Store Instructions for Memory Renaming Glenn Reinmany Brad Caldery Dean Tullseny Gary Tysonz Todd Austin
 

Summary: Classifying Load and Store Instructions for Memory Renaming
Glenn Reinmany Brad Caldery Dean Tullseny Gary Tysonz Todd Austin
yDepartment of Computer Science and Engineering, University of California, San Diego
zElectrical Engineering and Computer Science Department, University of Michigan
Microcomputer Research Labs, Intel Corporation
Abstract
Memory operations remain a significant bottleneck in dynam-
ically scheduled pipelined processors, due in part to the inabil-
ity to statically determine the existence of memory address depen-
dencies. Hardware memory renaming techniques have been pro-
posed to predict which stores a load might be dependent upon.
These prediction techniques can be used to speculatively forward a
value from a predicted store dependency to a load through a value
prediction table. However, these techniques require large, time-
consuming hardware tables.
In this paper we propose a software-guided approach for iden-
tifying dependencies between store and load instructions and the
Load Marking (LM) architecture to communicate these dependen-
cies to the hardware. Compiler analysis and profiles are used to
find important store/load relationships, and these relationships are

  

Source: Austin, Todd M. - Department of Electrical Engineering and Computer Science, University of Michigan
Calder, Bradley - Department of Computer Science and Engineering, University of California at San Diego
Sair, Suleyman - Department of Electrical and Computer Engineering, North Carolina State University

 

Collections: Computer Technologies and Information Sciences; Engineering