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Summary: The Location Consistency Memory Model and Cache Protocol:
Speci cation and Veri cation
Charles Wallace 1 , Guy Tremblay 2 , and Jose N. Amaral 3
1 Computer Science Dept., Michigan Technological University, Houghton, MI, USA
2 Dept. d'informatique, Universite du Quebec a Montreal, Montreal, QC, Canada
3 Computing Science Dept., University of Alberta, Edmonton, AB, Canada
Abstract. We use the Abstract State Machine methodology to give formal operational semantics for
the Location Consistency memory model and cache protocol. With these formal models, we prove that
the cache protocol satis es the memory model, but in a way that is strictly stronger than necessary,
disallowing certain behavior allowed by the memory model.
1 Introduction
A shared memory multiprocessor machine is characterized by a collection of processors that exchange infor-
mation with one another through a global address space [1, 6]. In such a machine, processors access memory
locations concurrently through standard read and write instructions. Shared memory machines have various
bu ers where data written by a processor can be stored before it is shared with other processors. Thus,
multiple values written to a single memory location may coexist in the system. For instance, the caches of
various processors might contain di erent values written to the same location.
The programs running on a shared memory machine are a ected by the order in which memory operations
are made visible to processors (which previous write operations are currently visible). A memory consistency
model is a contract between a program and the underlying machine architecture that constrains the order
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