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EnergyEfficient Design for Highly Associative Instruction Caches in NextGeneration Embedded Processors
 

Summary: Energy­Efficient Design for Highly Associative Instruction Caches in
Next­Generation Embedded Processors
Juan Luis Aragon Dan Nicolaescu Alex Veidenbaum Ana­Maria Badulescu
Center for Embedded Computer Systems
University of California at Irvine
{jlaragon, dann, alexv}@cecs.uci.edu
Abstract
This paper proposes a low-energy solution for CAM-
based highly associative I-caches using a segmented word-
line and a predictor-based instruction fetch mechanism.
Not all instructions in a given I-cache fetch are used due
to branches. The proposed predictor determines which in-
structions in a cache access will be used and does not fetch
any other instructions. Results show an average I-cache en-
ergy savings of 44% over the baseline case and 6% over the
segmented case with no negative impact on performance.
1. Introduction
Embedded processors routinely use multiple instruction
issue to increase performance. This leads to higher energy
consumption due to the presence of additional resources and

  

Source: Aragón Alcaraz, Juan Luis - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia

 

Collections: Computer Technologies and Information Sciences