Summary: Rethinking Hardware (and Software) for Disciplined Parallelism
Sarita V. Adve, Professor, Department of Computer Science, University of Illinois at Urbana-Champaign.
Area: "Home and business computing," but the position below applies to other platforms as well.
The problem: A fundamental obstacle to popular parallel programming is the lack of robust, general-purpose parallel
programming models. Current models are not only conceptually more difficult to understand than the sequential model,
but require abandoning decades of advances at the core of robust sequential software engineering practices (e.g., safety,
modularity, composability). Threads-based shared-memory, arguably the most widely used model, is known to be
difficult to program, debug, and maintain due to data races, ubiquitous non-determinism, etc. Even the most
fundamental property of "what value a shared-memory read may return" (a.k.a. the memory model) is notoriously
difficult to specify - recent efforts on language memory models have produced very complex semantics (Java) or
abandoned key safety and security features (C++) . We claim that building our systems on a foundation where it is
so difficult to specify even this fundamental property is at best questionable. We take the position that we must rethink
the way we both express and implement parallelism from the ground up, and together for both software and hardware.
The opportunity: Pessimists might abandon shared-memory; we believe the problem is not with shared-memory per se
(which has well-known advantages), but in our models allowing undisciplined, "wild" shared-memory interactions.
Some may argue that the programming model should be left to our software colleagues; however, the memory models
mess today could partly be attributed to such a software-oblivious hardware approach. We propose that a key part of a
future architecture research agenda should be centered on work with software colleagues to co-design (1) general-
purpose disciplined parallel programming models; (2) disciplined and expressive software and hardware interfaces for
these models; and (3) efficient implementations that fully exploit the information in these disciplined models and