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Estimation of the Weighted Maximum Switching Activity in Combinational CMOS Circuits Fadi A. Aloul andAssim Sagahyroon

Summary: Estimation of the Weighted Maximum Switching Activity in Combinational CMOS Circuits
Fadi A. Aloul andAssim Sagahyroon
Department of Computer Engineering, American University of Sharjah, U.A.E.
{faloul, asagahyroonj@aus.edu
Abstract - To achieve high reliability in VLSI designs, estimation of [26], a statistical approach based on the asymptotic theory of extreme or-
the maximum power dissipation during the design cycle is becoming der statistics was presented. The method is based on the theory of ex-
important. In previous work, it was shown that maximizing dissipa- treme order statistics applied to the probabilistic distributions of the
tion is equivalent to maximizing gate output activity, appropriately cycle-by-cycle power consumption, the maximum likelihood estimation,
weighted to account for differing load capacitances. Recent advances and the Monte-Carlo simulation.
in Boolean Satisfiability (SAT) models and algorithms have made it Recent years have seen a remarkable growth in the use of Boolean
tempting to use satisfiability-based techniques in solving various Satisfiability (SAT) models and algorithms for solving various problems
VLSI design-related problems such as verification and test genera- in Electronic Design Automation (EDA). This is mainly due to the fact
tion. SAT solvers have also been extended to handle 0-1 integer lin- that SAT algorithms have seen tremendous improvements in the last few
ear programming (ILP) problems. In this paper, we present an ILP- years, allowing larger problem instances to be solved in different applica-
based solution to compute the maximum weighted activity of combi- tions domains [2, 9, 14, 17, 27]. Such applications include formal verifi-
national circuits. The problem is formulated as an ILP instance and cation [3], FPGA routing [19], global routing [1], logic synthesis [16],
the new SAT-based ILP solvers are used to find an estimate for the and sequential equivalence checking [4]. SAT has also been extended to
power dissipation. For performance comparison, the problem is also a variety of applications in Artificial Intelligence including other well-
solved using generic ILP solvers. The validity of the proposed ap- known NP-complete problems such as graph colorability, vertex cover,
proach is demonstrated using benchmarks from the MCNC suite. and Hamiltonian path [6].


Source: Aloul, Fadi - Department of Computer Engineering, American University of Sharjah


Collections: Engineering