| | |
Summary: An O(log2N) parallel algorithm for output queuing
Amit Prakash Sadia Sharif Adnan Aziz
Department of Electrical and Computer Engineering
The University of Texas at Austin
{prakash, sharif, adnan}@ece.utexas.edu
Abstract--Output queued switches are appealing because they
have better latency and throughput than input queued switches.
However, they are difficult to build: a direct implementation of an
N × N output-queued switch requires the switching fabric and
the packet memories at the outputs to run at N times the line rate.
Attempts have been made to implement output queuing with slow
components, e.g., by having memories at both inputs and outputs
running at twice the line rate. In these approaches, even though
the packet memory speed is reduced, the scheduler time complex-
ity is high -- at least (N). We show that idealized output queuing
can be simulated in a shared memory architecture with (3N - 2)
packet memories running at the line rate, using a scheduling algo-
rithm whose time complexity is O(log2
N) on a parallel random
access machine (PRAM). The number of processing elements and
|
