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Low Power Commutator for Pipelined FFT Processors , T. Arslan1,2
 

Summary: Low Power Commutator for Pipelined FFT Processors
Wei Han1
, T. Arslan1,2
, A.T. Erdogan1,2
and M. Hasan1
1
School of Engineering and Electronics, University of Edinburgh, Edinburgh EH9 3JL, UK
2
Institute for System Level Integration, Livingston EH54 7EG, UK
{W.Han,T.Arslan,Ahmet.Erdogan}@ee.ed.ac.uk
Abstract--This paper proposes a low power commutator
architecture for the implementation of radix-4 based pipelined
Fast Fourier Transform processor. The architecture is based
on dual port RAM blocks and exploits the interconnection
topology among these blocks for low power implementation.
The paper presents the commutator architecture, describes the
design methodology and evaluation environment, and provides
implementation results showing that the new commutator
achieves up to 58% power saving for 256-point and 128-point
FFTs as compared to previous commutator architectures.

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering