Summary: ©2001 Open SystemC Initiative (OSCI)
An Introduction to System Level
Modeling in SystemC 2.0
By Stuart Swan, Cadence Design Systems, Inc.
SystemC is a new modeling language based on C++ that is intended to enable system level design and IP
exchange. This tutorial paper briefly reviews the hardware modeling features available in SystemC 1.0 and then
introduces the new system level modeling features in SystemC 2.0. A small design example is presented that
demonstrates how the new features facilitate system level design tasks such as communication refinement
and mapping of design specifications to hardware and software implementations. Also discussed is how the
new modeling features enable a wide variety of models of computation to be cleanly expressed within SystemC.
The emergence of the system-on-chip (SoC) era is creating many new challenges at all stages of the design
process. At the systems level, engineers are reconsidering how designs are specified, partitioned and verified.
Today, with systems and software engineers programming in C/C++ and their hardware counterparts working
in hardware description languages such as VHDL and Verilog, problems arising from the use of different
design languages, incompatible tools and fragmented tool flows are becoming common.
Momentum is building behind the SystemC language and modeling platform, based on C++, as the solution for
representing functionality, communication, software and hardware at various system levels of abstraction. The