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The continuing decrease in feature size and increase in chip density is causing leakage current to be a major contributor to
 

Summary: Abstract
The continuing decrease in feature size and increase in chip
density is causing leakage current to be a major contributor to
power dissipation in integrated circuits. A viable approach to
the reduction of leakage current is to use power cut-off or gat-
ing techniques. In power gating, a PMOS sleep transistor is
used to turn-on or turn-off the source to the circuit block.
In combinational circuits, the maximum power up current de-
pends only on the input vector that wakes up the circuit from
its sleep mode. In this work, we formulate the problem of es-
timating the maximum power-up current as an integer linear
programming (ILP) problem and use advanced Boolean satis-
fiability (SAT) and generic ILP solvers. Results indicate that
generic ILP solvers are very useful in estimating the maxi-
mum power-up current.
1. Introduction
The recent surge in the deployment and utilization of portable
electronic devices has brought power dissipation to the fore-
front as a major design concern. Leakage power is becoming
a growing problem as technology scales for battery-operated

  

Source: Aloul, Fadi - Department of Computer Engineering, American University of Sharjah

 

Collections: Engineering