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Summary: 394 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 4, NO. 3, MAY 1993
The Design of a Neuro-Microprocessor
John Wawrzynek, Krste AsanoviC, and Nelson Morgan, Senior Member, IEEE
Abstract- This paper presents the architecture of a neuro-
microprocessor.This processor was designed using the results of
careful analysis of ourset of applications andextensive simulation
of moderate-precisionarithmetic for back-propagationnetworks.
We present simulated performance results and test-chip results
for the processor. This work is an important intermediate step in
the development of a connectionist network supercomputer.
I. INTRODUCTION
E are engaged in the development of a connectionist
Wnetwork supercomputer. This computer is targeted for a
peak performance of 1011connections per second for networks
with up to a million units and a billion connections. It will
include specialized sensor and actuator interfaces for interac-
tion with real-time processes. We feel that this combination
of large networks and real-world interaction is critical to the
development of large neural network applications and has the
potential of enabling new science.
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