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Summary: DiCo-CMP: Efficient Cache Coherency in Tiled CMP Architectures
Alberto Ros, Manuel E. Acacio, Jos´e M. Garc´ia
Departamento de Ingenier´ia y Tecnolog´ia de Computadores
Universidad de Murcia
Campus de Espinardo S/N, 30100 Murcia, Spain
{a.ros,meacacio,jmgarcia}@ditec.um.es
Abstract
Future CMP designs that will integrate tens of processor
cores on-chip will be constrained by area and power. Area
constraints make impractical the use of a bus or a crossbar
as the on-chip interconnection network, and tiled CMPs or-
ganized around a direct interconnection network will prob-
ably be the architecture of choice. Power constraints make
impractical to rely on broadcasts (as Token-CMP does)
or any other brute-force method for keeping cache coher-
ence, and directory-based cache coherence protocols are
currently being employed. Unfortunately, directory proto-
cols introduce indirection to access directory information,
which negatively impacts performance. In this work, we
present DiCo-CMP, a novel cache coherence protocol es-
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