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IEEE DESIGN&TEST OF COMPUTERS 1 Leakage Minimization Technique
 

Summary: IEEE DESIGN&TEST OF COMPUTERS 1
Leakage Minimization Technique
For Nanoscale CMOS VLSI
Based On Macro-Cell Modeling
Kyung Ki Kim, Yong-Bin Kim, Minsu Choi , and Nohpill Park
Department of Electrical and Computer Engineering
Northeastern University, Boston, MA, USA
Department of Electrical and Computer Engineering
University of Missouri-Rolla, Rolla, MO, USA
Department of Computer Science
Oklahoma State University, Stillwater, OK, USA
kkkim@ece.neu.edu, ybk@ece.neu.edu, choim@umr.edu, and npark@cs.okstate.edu
Abstract
This paper proposes a new heuristic approach to determine the input pattern that minimizes leakage
currents of nanometer CMOS circuits during sleep mode considering stack and fanout effect. The
proposed approach uses a new precise macro-modeling of leakage current considering subthreshold
leakage, gate tunneling leakage, body effect, stack effect, and fanout effect. The macro-model is developed
for every gate in the library designed using 45nm BSIM4 model of Berkeley Predictive Technology Model
(BPTM). The methodology applies to ISCAS85 benchmark circuits, and the experimental result shows
that the proposed methodology using the proposed macro-model are within 4% difference comparing to

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering