Summary: A Hierarchical VLSI CAD Tool for Circuit
Placement
Shawki M. Areibi
University of Guelph, School of Engineering
Guelph, Ontario, Canada, N1G 2W1
phone (519) 884319 x3819, email sareibi@uoguelph.ca
Motivation
Due to the rapid growth of technolo-
gies, System-on-Chip (SoC) have
started to become a key issue in to-
day's electronic industry. Also, in to-
days deep sub-micron designs, the
interconnect is responsible for more
than 90% of the signal delay in a chip.
This project presents a new approach
for dealing with the high complexity of
ASIC design.
Introduction
The size of standard-cell placement
problems is increasing at a substan-

Source: Areibi, Shawki M - School of Engineering, University of Guelph

Collections: Engineering