Summary: To appear in Proceedings of SPAA­9 (June, 1997)
Using Speculative Retirement and Larger Instruction Windows to Narrow the
Performance Gap between Memory Consistency Models \Lambda
Parthasarathy Ranganathan, Vijay S. Pai, and Sarita V. Adve
Department of Electrical and Computer Engineering
Rice University
Houston, Texas 77005
fparthas---vijaypai---saritag@rice.edu
Abstract
This paper studies techniques to improve the performance
of memory consistency models for shared­memory multi­
processors with ILP processors. The first part of this pa­
per extends earlier work by studying the impact of current
hardware optimizations to memory consistency implementa­
tions, hardware­controlled non­binding prefetching and spec­
ulative load execution, on the performance of the processor
consistency (PC) memory model. We find that the opti­
mized implementation of PC performs significantly better
than the best implementation of sequential consistency (SC)
in some cases because PC relaxes the store­to­load ordering

Source: Adve, Sarita - Department of Computer Science, University of Illinois at Urbana-Champaign

Collections: Computer Technologies and Information Sciences