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Scalable Directory Organization for Tiled CMP Architectures Alberto Ros, Manuel E. Acacio, Jose M. Garcia
 

Summary: Scalable Directory Organization for Tiled CMP Architectures
Alberto Ros, Manuel E. Acacio, Jos´e M. Garc´ia
Departamento de Ingenier´ia y Tecnolog´ia de Computadores
Universidad de Murcia
{a.ros,meacacio,jmgarcia}@ditec.um.es
Abstract
Although directory-based cache coherence protocols are
the best choice when designing chip multiprocessor archi-
tectures (CMPs) with tens of processor cores on chip, the
memory overhead introduced by the directory structure may
not scale gracefully with the number of cores. In this work,
we show that a directory organization based on duplicating
tags, which are distributed among the tiles of a tiled CMP
with a fine-grained interleaving, is scalable. That is to say,
the size of each directory bank is independent on the number
of tiles of the system. Moreover, based on this directory orga-
nization we propose and evaluate the implicit replacements
mechanism which leads to savings of up to 32% in terms of
number of messages in the interconnection network.
Keywords: Tiled chip multiprocessors, cache coherence, di-

  

Source: Acacio, Manuel - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia

 

Collections: Computer Technologies and Information Sciences