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perform full reachability in Table 2. The time taken to perform model checking for all the cases are listed in
 

Summary: perform full reachability in Table 2. The time taken to
perform model checking for all the cases are listed in
Table 5.
We found that verification of certain properties took a
longer time than others. For example, for the property
listed in Table 3 could be completed in no time for the five
processor­cache configuration (Case V of Table 5). The
verification time for the five processor­cache
configuration is listed in Table 6. Note that the CTL time
is not the time taken to check this property `stand alone',
i.e., fixed point computations of other properties are
available.However, properties that check for deadlock and
livelock conditions, listed in Table 4, took a longer time to
complete. Table 7 gives the time taken to model check the
same property for processor B for the system having two
to five processors.
Within the same processor­cache configuration, the
number of fixed point computations for the above
properties were different. As the system is prioritized, and
hence not symmetric, the BDD size in the fixed point

  

Source: Aziz, Adnan - Department of Electrical and Computer Engineering, University of Texas at Austin

 

Collections: Computer Technologies and Information Sciences